1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method for the same.
2. Description of the Related Art
In recent years, thinner semiconductor chips are desired for mounting in a card-shaped thin package and providing a small mounted area of multiple semiconductor chips. However, wafer cracks or underside chipping may occur when transferring or dicing individual semiconductor chips, which are obtained by dicing a thin wafer provided by grinding the side (underside) opposing a device formed wafer side.
Dicing before grinding (DBG) methodology has been proposed as a method of preventing, to the utmost, wafer cracks or underside chipping due to thinned semiconductor chips (see Japanese Patent Application Laid-open 2002-118081, Japanese Patent Application Laid-open 2003-147300).
A semiconductor device 110 fabricated through the DBG methodology is shown in FIG. 1A, and a semiconductor device 120 is shown in FIG. 1B. The semiconductor device 110 shown in FIG. 1A is made up of a wiring substrate 106, a first and a second semiconductor chip 101a and 101b, a spacer 113, die bonding sheets (material) 104, and wires 112a, 112b connected to the first and the second semiconductor chip 101a and 101b. The first semiconductor chip 101a mentioned above has the die bonding sheet 104 on a first main surface opposing the wiring substrate 106, and a semiconductor element is formed on a second main surface opposing the first main surface. Accordingly, the second semiconductor chip 101b mentioned above has the die bonding sheet 104 on a third main surface opposing the wiring substrate 106, and a semiconductor element is formed on a fourth main surface opposing the third main surface. The die bonding sheet 104 having the same width as the spacer 113, which is sandwiched between the first and the second semiconductor chip 101a and 101b, is bonded to the first main surface opposing the wiring substrate 106. The first semiconductor chip 101a is mounted on the wiring substrate 106 via the die bonding sheet 104 formed on the first main surface. The second semiconductor chip 101b is adhered so that the third main surface opposes the first semiconductor chip 101a and that the spacer 113 is sandwiched therebetween.
A earlier technology fabrication method for the semiconductor device 110 is explained forthwith while referencing the process drawings of FIG. 2A to 2G and FIG. 3A to 3F.    (i) To begin with, as shown in FIG. 2A, semiconductor chips 101, which are obtained by being divided into diced shapes through the DBG methodology, are mounted on a surface protection sheet 102 so that the device formation face (the first or the third main surface) opposes the surface protection sheet 102.    (ii) Next, the die bonding sheet 104 is mounted on the semiconductor chips 101 as shown in FIG. 2B, and protruding portions 104c of the die bonding sheet 104 are removed as shown in FIG. 2C.    (iii) After turning the die bonding sheet over as shown in FIG. 2D, the die bonding sheet 104 is bonded on a sheet 108 so that the sheet 108 opposes the die bonding sheet 104. Afterwards, by peeling off the surface protection sheet 102, the adhesion faces of the respective semiconductor chips 101 are changed to the side of the sheet 108, and are joined to the die bonding sheet 104.    (iv) The semiconductor chip 101 with the die bonding sheet 104 is irradiated with ultraviolet light using a earlier technology method as shown in FIG. 2E. Consequently, an ultraviolet irradiated portion of the die bonding material 104b is hardened to be integrated with the sheet 108. Meanwhile, the remaining portion of the die bonding sheet 104 that was not irradiated since it is behind the semiconductor chip 101 maintains viscosity that allows it to be peeled off.    (v) This allows only each semiconductor chip 101 with the die bonding sheet 104 to be picked up when picking up the semiconductor chip 101 in the direction of the arrow using a transfer collet (not shown in the drawing) as shown in FIG. 2F.    (vi) A semiconductor chip 101 is mounted as the first semiconductor chip 101a on the wiring substrate 106 via the die bonding sheet 104 as shown in FIG. 3A. A spacer 113a is mounted on the first semiconductor chip 101a via the die bonding sheet 104 as shown in FIG. 3B. At this time, the spacer 113a with a predetermined width is mounted so as to secure a clearance d between the first semiconductor chip 101a and the second semiconductor chip 101b as shown in FIG. 3D. This prevents the wire 112a from being in contact with the die bonding sheet 104a during wire bonding, which is explained later.    (vii) The first semiconductor chip 101a is bonded with a wire 112a as shown in FIG. 3C.    (viii) The second semiconductor chip 101b is mounted on the first semiconductor chip 101a via the spacer 113a and the die bonding sheet 104 as shown in FIG. 3D.    (iv) The second semiconductor chip 101b is bonded with a wire 112b as shown in FIG. 3E.    (x) Afterwards, the semiconductor device 110 is fabricated as shown in FIGS. 3F and 1A by encapusulating with a encapusulating material 111.
However, in the step of picking up each semiconductor chip 101 shown in FIG. 2F, it is not easy to peel the unhardened portion of the die bonding sheet 104 off the hardened portions 104b of the die bonding sheet merged with the sheet 108. In other words, it is difficult to pick up selectively each semiconductor chip 101 adhered to the die bonding sheet 104.
To solve this problem, by a earlier technology, the semiconductor chip 101 is pushed upwards from below the sheet 108 by a needle 114 or the like as shown in FIG. 2G, thereby relaxing and allowing the sheet 108 to be peeled off and then removing the hardened portions 104b of the die bonding sheet.
Also, according to earlier technology, since it is difficult to control the location of the die bonding sheet 104, the die bonding sheet 104 is adhereed across the entire undersides (the first or the third main surfaces) of the semiconductor chips 101. As a result, the die bonding sheet 104 adhered to the underside of the second semiconductor chip 101b protrudes from the spacer 113a, as shown in FIG. 3D. A thick spacer 113a is formed so as to prevent the wire 112a from being in contact with this protruding die bonding sheet 104a. Consequently, the greater the number of wiring layers, the thicker the semiconductor device.